As the gap between processor and memory
speeds continuous to widen, methods for evaluating memory system designs
before they are implemented in hardware are becoming increasingly important.
Although many analytical models are used in advance to evaluate the performance
of the bus-protocol that maintains the coherence of the same data in all
caches for the shared-memory multiprocessors, the inevitable use of simplified
assumption for analysis on the computer system that has increasing complexity
causes certain limitation in the predetermined conditions of the analytical
results. The paper introduces the development, implementation and future
work for a trace-driven memory simulator for shared-memory multiprocessors.
In practice of the simulator, it provides a technology for simulating computer
system and is able to evaluate the desired system performance for serving
as a reference for the decision on the adoption or modification of the
system, with the objectives to increase production efficiency and save
have been sent back to the respective